In today’s technologies, it is critical to monitor power supply variations due to their negative impact on performance and integrity of the system. These variations are difficult to estimate during the design phase due to their strong dependence on various parasitic elements, both on-chip and off-chip as well as process dependence of local switching activity. Therefore on-chip power supply monitoring is required to provide feedback to the design flow or provide inputs to any mechanism that actively compensates for power supply noise errors. Interestingly, some of these power supply fluctuation characteristics have been exploited by various iDDT test techniques for defect screening. In cryptographic applications, power consumption variations seen off-chip are a rich soul-ce of information for intruders to obtain secret or keying materials from the system. Differential Power Analysis (DPA) technique uses statistical functions to analyze the power consumption and extracts the secret keys from the cipher systems. Consequently, this side-channel information needs to be masked to make it very difficult or practically impossible to perform power analysis on the secured system. In this work, we propose an on-chip monitoring and DPA countermeasure solutions that can be used concurrently for these allied applications. The circuits are designed to measure multiple power supply parameters, include area under voltage variation waveform, peak voltage over time and undershoot/overshoot detection, and provide protection against DPA attack. The monitoring circuit can be calibrated for process tolerant and can be used for characterization, productions as well as on-line testing. The DPA countermeasure circuit has been verified to work with different set of process parameters. These circuits can be integrated to existing logical or cryptographic cores at the final design stage with minimal impact. The circuits were implemented in 0.18 micron process and the results from detailed layout level simulations are presented in this work.